library verilog;
use verilog.vl_types.all;
entity EEPROM is
    generic(
        JC              : integer := 15;
        JMP             : integer := 14;
        MOV             : integer := 13;
        MVI             : integer := 12;
        INC             : integer := 11;
        ADD             : integer := 10;
        SUB             : integer := 9;
        I_AND           : integer := 8;
        I_OR            : integer := 7;
        SC              : integer := 6;
        CC              : integer := 5;
        PUSH            : integer := 4;
        POP             : integer := 3;
        \IN\            : integer := 2;
        \OUT\           : integer := 1;
        NOP             : integer := 0
    );
    port(
        address         : in     vl_logic_vector(7 downto 0);
        data            : out    vl_logic_vector(7 downto 0)
    );
end EEPROM;
